As demands in the semiconductor industry call for further miniaturization and performance enhancement of electronic systems, billions of transistors are now interconnected with tens of kilometers of wires that packed into an area of square centimeters. The complexity of the multi metallization levels of back-end-of-line (BEOL) brings challenges such as the need to reliably process BEOL dielectrics during various processing stages.
During semiconductor fabrication, unwanted surface irregularities can occur across the topological surface of a surface film of a semiconductor wafer. In some cases, large elevation disparities develop between different device regions of a BEOL dielectric layer or level during various processing stages. For example, during the fabrication of integrated circuit (IC) devices having memory regions and non-memory regions, non-volatile memory structures such as magnetoresistive memories may be embedded within multiple inter-level dielectric (ILD) layers. In this instance, the memory structures may be formed in the memory region of an ILD level, thereby resulting in a large step height between the memory region and non-memory region of the ILD level. The difference in surface topology may be transferred to the subsequent BEOL dielectric layer disposed over these regions, which translates to large elevation disparities across the surface topology of the BEOL dielectric layer. If left unattended, such surface irregularities can lead to fabrication defects. This often necessitates the planarization of BEOL dielectrics prior to further processing steps.
Chemical mechanical polishing (CMP) is a process commonly employed to remove surface irregularities of a surface film by removing excess surface material. However, conventional CMP processes are unreliable for planarizing topological surfaces with large elevation disparities due to end-point control limitations. For example, performing a CMP process to remove a large surface elevation in one portion of a BEOL dielectric layer may lead to over-polishing in unelevated portions of the BEOL dielectric layer.
The present disclosure relates to improving control and uniformity of planarization processes across different device regions during fabrication of embedded memory applications.